In our last podcast on 3D IC architecture workflows, we discussed how a system or microarchitectures determine how to partition a device’s functionality. Today, we will discuss what a 3D IC physical design workflow looks like, from prototyping and planning through system technology, co-optimization, and through to substrate routing and design verification.
There has been much growth and development in advanced heterogeneous packaging in the past several years. After defining the architecture, what are the typical design flow steps recommended or used for multi-die and chiplet heterogeneously integrated assemblies?
Managing complex interconnect design verification challenges
For discussion purposes, “substrate” represents the range of interconnect systems that fall under the IC packaging domain. Challenges when designing organic substrates differ significantly from those designing silicon interposers. The macro level offers similarities in defining and implementing the designed conductivity regardless of the interconnect technology.
Engagement with customers is typically at two points:
- Very early: when planning the design process and conductivity is defined
- Late: when customers are working to verify complex 2.5D or 3D IC system
As we all know, the days of managing a single-die package with a spreadsheet are long gone. Customer concern with conductivity grows alongside increasing artificial intelligence (AI) and high-performance compute silicon interposer designs with two to eight high-bandwidth memories (HBMs), fan-out wafer-level packaging, embedded bridge technology and system in package type designs. Engaging early to identify is solution is critical to help manage the complex interconnect challenges.
Interconnect system considerations in the design flow
The interconnect between the various devices is also an important consideration. A physical representation of the multiple chiplets or the die involved, along with the platform these devices will sit on. Each discipline uses its own tool and data format. The silicon team uses a set of placing route tools or a custom layout tool to design the die. And it will have, for the rest of the system, that appears somewhat like a black box. But that black box has to interface with a package or an interposer. The interposer team needs to know what the interface looks like from a netlist perspective and the physical bump layout. Tools can consume the information in whatever format it may be available, but the challenge comes when things change – how does each tool get updated? Some formats are more easily passed back and forth between the tools, but it’s an important consideration when thinking about design flows.
Managing disparate data sources in chiplet solutions
Disparate data sources is a growing challenge with interposer design related to silicon or chip design. A company using chiplets and designing their silicon may have input in multiple formats between the chiplet provider, silicon, and interposer. How do they combine the data, evaluate it, and use it to manage conductivity?
The challenge of not having to reimplement, redesign, and recapture the design elements from their native format and use them as they are becomes a critical part of the design process. This challenge is particularly concerning for those worried about this early in the design process and not late in the verification stage.
So, the substrate design team needs a solution that can quickly and accurately handle the multiple data formats without translating data into something else and bringing it into a single cohesive system representation and netlist.
Early planning for design verification of multi-die systems
Design verification teams for multi-die systems work with the silicon team to verify the various interfaces between memory or standard interfaces like USB or PCI-E. The verification team uses the Verilog design representation that’s verified with a comprehensive test bench for multiple interfaces. Design teams want to import it and use it as is. Having a solution that works with that input as-is is crucial. Teams can get the standard parts like memory from those vendors, the chip design from the chip team, and then the netlist from the verification team that brings it all together.
Verifying the independent pieces at the end of the design cycle leaves the design team to work with fixed data that they must adapt to figure out whether it connects correctly. And while we can do that, they often find issues very late in the design cycle. So, whenever possible, teams should consider late-stage design verification throughout the design and use a planning tool to manage the data. The golden netlist, as we often call it, is no longer kept in a spreadsheet but rather in a planning tool that replaces the spreadsheet.
Combining all these pieces enables early analysis and collaboration, often referred to as system-technology co-optimization (STCO) for early analysis and trade-offs. Using a centralized planning tool and the integrations available makes it easy for design teams to make intelligent decisions early in the design cycle. And as the design matures, the questions about correctness can be answered as part of the design cycle and not waiting until the end.
Physical verification of individual pieces and the total solution
One of the other aspects of the 3D IC design flow is the physical verification and the differences between the physical verification of individual pieces and the total solution. Teams can verify the interposer or the package, but what about when they are all together? Are they connected and lined up correctly?
For example, when teams are doing a stacked substrate design, there’s almost always a horror story where part of the layout is complete. Still, someone interpreted one of the specifications as pins up or down instead of the correct orientation. And they ended up building and manufacturing a piece mirrored from the die or the interposer. How do you prevent these design errors things from happening?
Teams need comprehensive verification of the entire assembly:
- the die
- the interposer
- the package
- the PCB (if it’s available)
After being put together in a single environment, the assembly needs verification to ensure all of the pieces line up.
Assembly verification and system-level LVS
How do companies account for die scaling and package bump compensation factor so that it works when everything is put together and manufactured?
As the most active topic in 2.5D and 3D IC design, we know a comprehensive set of planning tools enables teams to ensure proper bump alignment and verify the correctness of net names to avoid conductivity shorts upon connection. Referred to as system layout versus schematic (LVS) flow, it involves doing LVS of the entire system to check the various design domains. The package design may call a set of net clock CLK. The interposer team has them, where the clock signals are similar names but not the same. And then the die calls them yet again something else.
How do teams validate the connection from the package bumped, BPA bumped through the package to the interposer C4 to the die, and then that the clock connection from the BGA to the die is correct through all of the net name transitions, interconnect from the various package and interposer layers?
The Siemens planning and verification platform allows you to do that. Finding those types of problems when you have a multi-substrate, multi-die system; finding those before you fabricate it is imperative because it’s costly when you don’t.
Where to focus first: assembly verification
The most accessible place to start is assembly verification, the ability to take the package netlist and the silicon die, or multiple silicon dies and verify the system is correct. These verifications are typically straightforward and enable teams to find mistakes. When used early in the design cycle, teams don’t need the complete package implemented to find value in the verification because they can uncover simple “pins up, pins down” types of mistakes. By doing an overlaps check between the data, the silicon and the package, teams can verify the orientation is correct and that all the bumps are in the right spot. These checks are quick, high value-add and easy to do early in the design cycle. Setting up these checks early makes it easy to run them every time there’s an update from the silicon team. As the design matures and the implementation is done, adding LVS to the verification becomes very simple later in the design process. Assembly verification is an excellent place to start and allows teams to grow.
Want to learn more about the impact of 3D IC on physical design workflows? Listen to the podcast now, available on your favorite podcast platform.
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